For High Voltage (HV) NMOS fabricated with BiCMOS or BCDMOS technologies, low on resistance (Ron) and high breakdown voltage are two essential parameters. FIG. 1 illustrates one conventional HV NMOS structure, and FIGS. 2A and 2B show stages in forming the HV NMOS structure of FIG. 1. As shown in FIG. 1, The HV NMOS comprises an N-well and a P-well both implanted in a P-substrate. The NMOS includes a gate G composed of an oxide layer 11 and a poly-silicon layer 12, an N+ source pickup region S, and a drain pickup region D. For the conventional HV NMOS, the P-well is defined by N-well oxidation 20 and is side diffused under the N-well oxide 20 seen in FIG. 2A. An oxidation silicon step 21 is formed on the main surface after the N-well oxide 20 is removed as seen in FIG. 2B. In conventional devices, the channel length (P-well overlap with Poly) tends to be long in order to increase the mask misalignment margin and punch-through breakdown voltage.
The channel for conventional NMOS as seen in FIG. 1 is defined by the overlap portion of the P-well area and its side diffusion area with the gate electrode 12. Thus, the portion of the channel under the silicon step 21 is not flat, as indicated by the dotted line. The silicon step 21 is believed to hamper the electron flow along the channel to increase Ron. Also, the long channel further increases Ron.